1. Field of the Present Invention
The present invention generally relates to the field of microprocessors and more particularly to a method of handling register updates in an out of order processor.
2. History of Related Art
Out-of-order processors are well known in the field of microprocessor based computer systems. In an out-of-order processor, instructions may be executed in an order that differs from the program order of the instructions. Out-of-order execution is facilitated through the use of register renaming techniques and the storage of results in a temporary storage facility until the instruction is committed. The presence of special purposes bits such as sticky bits in a register complicates out-of-order execution because of the manner in which sticky bits are updated. Whereas conventional or non-sticky bits are generally updated each time the corresponding register is updated, sticky bits may be unaffected by operations that update other bits in the register. Some instructions leave the value of a sticky bit unchanged whereas other instructions explicitly set or clear the sticky bit. Conventional methods of handling out-of-order execution typically contemplate that a single bit of information provided by the instruction is sufficient to indicate the state in which the corresponding bit of a register should be after the instruction is committed. Thus, if the instruction provides a 0 associated with a particular register bit, the value of the register bit after the corresponding instruction is committed will be 0. In the case of a sticky bit, however, the state of the sticky bit after an instruction is committed is a function of the state of the sticky bit before the instruction was executed as well as the value of a corresponding bit of information in the instruction. It will be appreciated that this characteristic of sticky bits adds an additional layer of complexity in processors enabled to execute instructions out-of-order. To address the issues introduced by the presence of sticky bits, conventional processors typically incorporate complex commit circuitry to determine the type of instruction that is being executed. Once the instruction type is determined, the commit circuitry according to the prior art can interpret the data that is associated with the operation. As an example, a 0 data bit may indicate that the corresponding register bit is to be written with a 0 for one type of operation while a 0 in the same data bit location may simply indicate that the value of the corresponding register bit is to remain unchanged for another type of operation.
An example of a conventional commit circuit 600 according to the prior art is depicted in FIG. 6. In the depicted circuit, a set of data bits 602 and a set of control bit 604 comprise the input to commit function 600. The data bits 602 are routed in parallel through a set of functional circuits 606. Each function in the set of functional circuits 606 produces a corresponding output dependent on the value of the data bits 602. The output of each of the functions in the set of functional circuits 606 is routed to a multiplexer 608. The control bits 604 are decoded in a decoder circuit 610 to produce a select signal 612 that selects one of the set of functional circuits 606 in multiplexer 608. The output of the selected function then becomes the output of commit function 600 that is then committed to the appropriate register. It will be appreciated by those skilled in the field of microprocessor circuit design that the commit function 600 includes expensive and otherwise undesirable complexity that increases the die size of the microprocessor and can negatively impact processor performance. Therefore, it would be advantageous to design a system capable of committing operations and updating register bits (including sticky bits) in an out of order processor without requiring the presence of a complex and expensive logic circuit.
The issues identified above are in large part addressed by a method and processor that enable efficient management of multiple, out-of-order, speculative, and arbitrary updates to a register that includes xe2x80x9cstickyxe2x80x9d bits and xe2x80x9csummaryxe2x80x9d bits. Broadly speaking, the processor includes a register, an execution unit, a temporary result buffer, and a commit function circuit. The register includes at least one register bit and may include one or more sticky bits. Sticky bits as used herein, are special purpose register bits that, once set, will remain set until they are explicitly cleared by a special instruction. The execution unit is suitable for executing a set of computer instructions. The temporary result buffer is configured to receive, from the execution unit, register bit modification information provided by the instructions. The temporary result buffer is suitable for storing the modification information in set/clear pairs of bits corresponding to respective register bits of the register. The commit function stage includes a set of commit function circuits configured to receive the set/clear pairs of bits from the temporary result buffer when the instruction is committed. Each commit function circuit is suitable for generating an updated bit in response to receiving the set/clear pairs of bits. The updated bit is then committed to the corresponding register bit of the register.
Preferably, each commit function circuit is configured to generate a xe2x80x9c1xe2x80x9d if the set bit of the set/clear pair is asserted and further configured to generate a xe2x80x9c0xe2x80x9d if the clear bit of the set/clear pair is asserted. In one embodiment, each commit function circuit is configured to receive the existing value of the register bit from the register. The value of the updated bit equals the existing value if neither the set bit nor the clear bit of the set/clear pair is asserted. In one embodiment suitable for its simplicity, a commit function circuit includes an OR gate and an AND gate. The OR gate is configured to receive the existing value of the register bit and the set bit of the set/clear pair as inputs. The AND gate is configured to receive the output of the OR gate and the inverse of the clear bit as inputs. The output of the AND gate serves as the updated bit that is then recorded in the appropriate register bit of the register.
In the preferred embodiment, the temporary result buffer includes multiple entries. In this embodiment, each instruction is associated with a tag. The tag indicates the entry in the temporary result buffer where instruction information, including the register bit modification information, will be stored. In one embodiment, the processor is adapted to associate multiple instructions with a common tag such that multiple instructions share a common entry in the temporary result buffer. The processor and the execution unit are preferably configured to execute instructions out-of-order and speculatively to achieve optimal processor performance.
Utilizing the processor and the data processing system in which the processor is embodied, the invention further contemplates a method of managing register bit modification in an out-of-order capable processor. The method includes executing a set of instructions and recording register bit modification information provided by each of the instructions in set/clear pairs of bits that correspond to each of one or more register bits in the register. Thereafter, for each instruction in the set of instructions, the register bits are updated based on the modification information when the instruction is committed. Preferably the register bit modification information is recorded by storing the information in one of multiple entries in a temporary buffer. The selected entry in the temporary result buffer is preferably determined based upon a tag that corresponds to the instruction. Multiple instructions may correspond to the same temporary result buffer tag and, thereby, share a common entry in the result buffer. The updating of register bit information preferably includes generating an updated bit with a commit function circuit that is configured to receive the set/clear pair of bits as inputs. In a presently preferred embodiment, the updated bit is set to xe2x80x9c1xe2x80x9d if the set bit of the set/clear pair corresponding to the instruction being committed is asserted and xe2x80x9c0xe2x80x9d if the clear bit set/clear pair is asserted. If neither the set nor the clear bit is asserted, the existing value of the register bit prior to the updating function becomes the updated bit such that the register bit remains unchanged if neither the set bit nor the clear bit is asserted.